1. Field of the Invention
The present invention relates to a fast, high-resolution A/D converter.
2. Description of the Prior Art
A successive approximation type is often used in a middle- or high-speed A/D converter. In this system, an input voltage does not change until one conversion is finished. A sample/hold circuit is essential at an input end. An operable input frequency of the sample/hold circuit has an upper limit due to an acquisition time or signal feed through. In addition, a dynamic range of the sample/hold circuit is also limited because it is an analog circuit. A tracking type A/D converter as shown in FIG. 4 which does not require a sample/hold circuit is known.
The A/D converter shown in FIG. 4 compares an input voltage to be converted with a reference (zero) by a comparator 25 and controls a count direction of an up/down counter 26 in accordance with an output (of high level/low level) from the comparator 25. The counter 26 counts clock pulses CLK. A count output is converted into an analog signal by a D/A converter 27 and subtracted from the input. An output from the counter 26 obtained when the input voltage of the comparator 25 reaches substantially zero represents digital conversion data.
This system responds to a considerably high input frequency with respect to a small-amplitude input. The system, however, responds slowly to a large-amplitude input. In addition, since an output digital value always follows an input voltage due to count up/down, an output flutters by 1LSB. Also, resolution (a dynamic range) of the system is limited due to a problem of offset, linearity, or the like of the comparator 25 (operational amplifier). An upper limit of the resolution is about 12 bits.
A subranging A/D converter as shown in FIG. 5 is used especially in a high-resolution application. Referring to FIG. 5, an input voltage is sample-held by a sample/hold circuit 31 and supplied to, e.g., a flash A/D converter 33 via a subtractor 32. An output from the A/D converter 33 is supplied as upper bits to a latch circuit 37. Also, this output is converted into an analog voltage by a D/A converter 34 and supplied to the subtractor 32. The subtractor 32 outputs an error (difference) between the input and converted voltages. This difference is amplified with a predetermined gain by an amplifier 35 and supplied to a second A/D converter 36. An output from the A/D converter 36 is supplied as lower bits (subrange) via the latch circuit 37 together with the upper bits.
This subranging system is advantageous because a considerably high resolution is obtained by a combination of the A/D converters 33 and 36, and no error is produced due to the comparator 25 at the input side shown in FIG. 4.
In the subranging system shown in FIG. 5, since the A/D converters 33 and 36 operate sequentially, an operation speed is limited. In addition, as in the successive approximation system, the sample/hold circuit 31 is essential in this system. Therefore, the resolution of the system is substantially limited by the limitation of the dynamic range of the sample/hold circuit 31.